The present invention relates generally to semiconductor devices and more particularly to methods and apparatus for fabricating semiconductor devices using implantation to induce stress in an electrical device.
Many conventional semiconductor devices include metal-oxide-semiconductor field-effect transistor (MOSFET) and other transistor devices to perform a variety of functions, such as switching, amplification, and the like. As required switching speeds increase and as operating voltages levels decrease in semiconductor products, the performance of transistors within such products needs to be correspondingly improved. For instance, switching speed requirements of MOSFETs and other transistors continue to increase in order to facilitate faster and improved product performance. Moreover, as such devices increasingly find application within wireless communications systems, portable computers, and other low-power, low-voltage devices, MOSFETs and other devices increasingly must be adapted to operate using less power and at lower voltages.
The carrier mobility in a MOSFET device can have a significant impact on power consumption and switching performance. The carrier mobility is a measure of the average speed of a carrier (e.g., holes or electrons) in a given semiconductor, given by the average drift velocity of the carrier per unit electric field. Thus, improved carrier mobility can improve the switching speed of a MOSFET transistor. Moreover, improving the carrier mobility in the device can allow operation at lower voltages. This may be accomplished, in addition, by reducing the channel length and gate dielectric thickness in order to improve current drive and switching performance. However, reducing the gate dielectric thickness results in an increase in gate tunneling current, which in turn degrades the performance of the device by increasing off state leakage. In addition, decreasing gate length generally requires more advanced and expensive lithography technology.
Other attempts at improving carrier mobility in silicon MOSFET devices have included depositing silicon/germanium alloy layers between upper and lower silicon layers under compressive stress, in order to enhance hole carrier mobility in a channel region. However, such buried silicon/germanium channel layer devices have shortcomings, including increased alloy scattering in the channel region that degrades electron mobility, a lack of favorable conduction band offset which mitigates the enhancement of electron mobility and the need for large germanium concentrations to produce strain and thus enhanced mobility. Furthermore, such additional alloy layers and silicon layers are costly, adding further processing steps to the device manufacturing procedure. Thus, there is a need for methods and apparatus by which the carrier mobility and other electrical operational properties of MOSFET and other transistor devices may be improved so as to facilitate improved switching speed and low-power, low-voltage operation, without significantly adding to the cost or complexity of the manufacturing process.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention relates to semiconductor device fabrication, wherein selective implantation of one or more species are used to induce stress in electrical devices within a semiconductor chip. The induced stress may be used to modify the electrical behavior of the devices, such as by improving carrier mobility, silicidation, diffusion behavior, or other performance characteristics or fabrication processes.
The invention generally provides methods and apparatus for selectively inducing stress in a semiconductor device, wherein a first region of a substrate is implanted so as to induce stress in a second region. An electrical device is formed at least partially in the second region, wherein the induced stress therein may be advantageously employed to improve performance characteristics in a controlled fashion. In this manner, the invention may be employed, for instance, to induce stress (e.g., tensile or compressive) selectively in a channel region (e.g., or a portion thereof) in a MOSFET device, in order to improve carrier mobility. Furthermore, the particular species chosen for implantation in the first region may be selected according to the type of device in which stress is to be induced (e.g., PMOS or NMOS).
According to one aspect of the present invention, a method is provided for fabricating semiconductor devices. The method involves selectively implanting a first region in a substrate so as to induce stress in a second region in the substrate, and forming an electrical device in the substrate, at least a portion of the electrical device being in the second region. The first region may, but need not, be formed so as to underlie the second region, and may be implanted by forming a mask over a first portion of a top of the substrate in order to leave a second portion thereof exposed, and performing an ion implantation using the mask so as to implant the first region in the substrate below the exposed second portion. In order to conserve on processing steps, the implantation may be done using masks already used for other operations. For example, the implantation may be done using a dopant mask, also employed to selectively dope the substrate (e.g., to form source/drain regions and/or depletion type channel regions, etc.) using at least one of diffusion and implantation during formation of a MOSFET type electrical device. As another example, the mask used for implantation of the first region may also function as an etch mask used to form an isolation trench or other ancillary structures.
Various implantation species may be used for implanting the first region. For example, in one implementation of the method, the implantation may employ carbon, germanium, and/or oxygen using the mask to implant the first region in the substrate below the exposed second portion. Carbon may be used, for example, where it is desired to create a tensile stress in the first region. This stress, in turn, induces a stress (e.g., tensile or compressive) in the second region, depending on the configuration of the first and second regions in the substrate. Conversely, implantation of germanium or oxygen in the first region may be done to create a compressive stress therein. The induced stress in the second region may thus be engineered to advantageously affect the electrical operation of the device. For instance, compressive induced stress in the second region may be used to increase hole mobility in a PMOS channel region, whereas tensile induced stress may be employed to increase electron mobility in an NMOS type device.
Another aspect of the invention provides a semiconductor device, having first and second regions in a substrate. The first region is implanted so as to induce stress in the second region, and an electrical device or a portion thereof is provided in the second region. The first region may be located beneath at least a portion of the second region, or be near the second region in order to facilitate the induced stress effect therein. The electrical device may be, for example, a transistor with a source/drain region or a channel region formed within the second region, and the first region may be implanted with carbon, germanium, and/or oxygen so as to induce stress in the second region. Yet another aspect of the invention provides a method of improving carrier mobility in a channel region of a MOSFET device, which involves implanting a first region in a substrate so as to induce stress in a second region in the substrate, and forming at least a portion of the channel in the second region of the substrate.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.